1. Field of Invention
The present invention relates to a fabrication method for multilevel interconnects of a semiconductor device. More particularly, the invention relates to a method of fabricating a dual damascene structure.
2. Description of Related Art
In the development of semiconductor industry, an improvement in operation speed of the device has always been a technology that all semiconductor manufacturers are up to compete, as well as been a main criterion that consumers take into account when making a purchase. With a rapid development of an integrated circuit process, a resistance of a conductive line and a parasitic capacitance between the conductive lines are determined as two key factors among all factors for influencing the operation speed of the device. Accordingly, a metal layer having a low resistance, such as a copper layer can substitute an aluminum layer used in the conventional method for reducing the resistance of the conductive line. A low dielectric constant (k) material, such as a low k organic dielectric layer can substitute a silicon oxide layer used in the conventional method for reducing the parasitic capacitance between the conductive lines.
A typical metal interconnect process involves forming a metal plug in a dielectric layer, followed by forming an aluminum line over a substrate for connecting to the metal plug. Generally, a dual damascene technique is a metal interconnect process with a high reliability and low cost, while a material selection for the metal interconnect is not limited by etching process for the metal. Therefore, this technique is widely applied to the manufacture of the copper line to reduce the resistance of the conductive line, and to further improve the operation speed and quality of the IC device. As there is a demand for a high operation speed of the device, fabricating the dual damascene with the low k material layer has been practiced in the metal interconnect process of the semiconductor industry.
FIG. 1 is a schematic, cross-sectional diagram illustrating a conventional dual damascene structure. Referring to FIG. 1, a via opening 112 is formed in a dielectric layer 104, while a trench 110 is formed in a dielectric layer 108. The via opening 112 and the trench 110 are then filled with a metal layer 114 to form a dual damascene structure.
As a conventional means to control a depth of the trench 110, a silicon nitride layer 106 is formed between the dielectric layers 104 and 108 to serve as a stop layer during an etching process for forming the trench 110.
However, the silicon nitride layer 106 has a dielectric constant of about 7, so a large parasitic capacitance easily occurs at areas, such as corners 118 of the trench 110 and the via opening 112, where the silicon nitride layer 106 makes a direct contact with the metal layer 114. This leads to a resistance-capacitance (RC) time delay and affects an operation efficiency of the device.
Moreover, as an integration of the device increases, the parasitic capacitance between two metal layers becomes more serious. Therefore, in a deep sub-micron process and below, a low k material is commonly used to form an inter-metal dielectric (IMD) layer in order to reduce the RC time delay derived from the parasitic capacitance.
The photoresist layer is commonly made of a polymer, while the common low k material is the organic polymer. So, when a photoresist layer that patterns the trench 110 is removed, an oxygen plasma can damage the low k organic dielectric layers, 108 and 104. As a result, the low k organic dielectric layers, 108 and 104 on sidewalls of the trench 110 and the via opening 112 begin to absorb water, resulting a poisoned issue when the metal layer 114 is deposited.